Longreads
Semiconductor Packaging Technology
Wire bonding and flip-chip packaging represent two fundamental approaches to chip interconnection. While wire bonding offers simplicity and cost benefits, flip-chip allows ...
Scaling beyond 100nm – Nanoelectronics Era
As silicon and silicon dioxide reach their scaling limits, engineers turn to high-k materials, metal gates, and new device architectures like FinFETs ...
Scaling of CMOS: Microelectronics era
As CMOS technology shrank below 1 μm in the microelectronics era, high electric fields caused reliability issues like hot carrier effects. Techniques such ...
Editor's Choise
No items were found matching your selection.
Scaling of CMOS: Microelectronics era
As CMOS technology shrank below 1 μm in the microelectronics era, high electric fields caused reliability issues like hot carrier effects. Techniques such as LATID and Anti-Punch Through (APT) ...
Subscribe for the daily Newsletter
Our biggest stories, delivered to your inbox every day.