© All rights reserved. Powered by Florisera.

RSS Daily tech news
Featured image of microelectronic scaling

Scaling of CMOS: Microelectronics era

As CMOS technology shrank below 1 μm in the microelectronics era, high electric fields caused reliability issues like hot carrier effects. Techniques such as LATID and Anti-Punch Through (APT) were introduced to control these effects and extend the performance of shrinking devices.
Categories
Instagram
Visual Portfolio, Posts & Image Gallery for WordPress